10/20 上課教學-3

module top;

wire x_in1,x_in2,x_in3,x_in4;

wire y_out;

system_clock #200 clock1(x_in1);

system_clock #150 clock2(x_in2);

system_clock #100 clock1(x_in3);

system_clock #50 clock2(x_in4);

A01_4_Unit AH1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodulemodule

A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;

output y_out;

wire y1,y2;

and #1(y1,x_in1,x_in2);

and #1(y2,x_in3,x_in4);

nor #1(y_out,y1,y2);

endmodulemodule

system_clock(clk);

parameter PERIOD = 100;

output clk;reg clk;

initialclk = 0;

always

begin

#(PERIOD/4) clk = ~clk;

#(PERIOD/4) clk = ~clk;

#(PERIOD/4) clk = ~clk;

#(PERIOD/4) clk = ~clk;

end

always@(posedge clk)

if($time > 1000) #(PERIOD-1)$stop;

endmodule