11/17 [2bit比較器 behavior , RTL 和 gate_level]

2bit behavior compare

2bit RTL compare

2bit gate_level compare

11/11 加分考

10/27 考試前一個禮拜

10/20 上課教學-3

module top;

wire x_in1,x_in2,x_in3,x_in4;

wire y_out;

system_clock #200 clock1(x_in1);

system_clock #150 clock2(x_in2);

system_clock #100 clock1(x_in3);

system_clock #50 clock2(x_in4);

A01_4_Unit AH1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodulemodule

A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;

output y_out;

wire y1,y2;

and #1(y1,x_in1,x_in2);

and #1(y2,x_in3,x_in4);

nor #1(y_out,y1,y2);

endmodulemodule

system_clock(clk);

parameter PERIOD = 100;

output clk;reg clk;

initialclk = 0;

always

begin

#(PERIOD/4) clk = ~clk;

#(PERIOD/4) clk = ~clk;

#(PERIOD/4) clk = ~clk;

#(PERIOD/4) clk = ~clk;

end

always@(posedge clk)

if($time > 1000) #(PERIOD-1)$stop;

endmodule

10/20 上課教學-2

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;

output y_out;

wire y1,y2;

reg y_out,y1,y2;

always

begin

#1 y1=x_in1&x_in2;

#1 y2=x_in3&x_in4;

#1 y1=x_in1 nor x_in2;

end

endmodule

10/20 上課教學-1

module A01_4_Unit (y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;output y_out;
wire y1,y2;

and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule

10/13 好困難的作業

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
Add_half AH1(sum,c_out,a,b);
endmodulemodul
e Add_half(sum,c_out, a, b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodulemodule
system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/6 第二次課堂作業

p.q:
module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

10/6 轉換

今天換大教室 好開心!

希望一切順利~~

9/22課堂作業

module top;
wire a,b;
reg c;
System_clock #100 clock1(a);
System_clock #50 clock2(b);
always#1 c=a&b;
endmodulemodule System_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initialclk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if ($time>1000)#(PERIOD-1)$stop;
endmodule



是一次新的體驗

期待下次!